With increasing demands for advanced semiconductor transistor structures, the use of dopants to control conduction of charge carriers in the conduction channel of CMOS devices is reaching its limits. As CMOS devices are scaled to the nanometer regime, SOI structures including fully depleted (FD) and partially depleted (PD) structures have provided an evolutionary pathway for MOSFETS operating at low power. However, SOI devices can exhibit the problem of self-induced heating, which can be exacerbated by reduced charge mobility in a transistor channel region.
Mechanical stresses are known to play a role in charge carrier mobility which affects several critical parameters including Voltage threshold (VT) shift, drive current saturation (IDsat), and ON/Off current. The effect of induced mechanical stresses to strain a MOSFET device channel region, and the effect on charge carrier mobility is believed to be influenced by complex physical processes related to acoustic and optical phonon scattering. Ideally, an increase in charge carrier mobility will also increase a drive current.
For example, prior art processes have proposed lattice constant mismatch epitaxy to induce a stress on channel regions to form strained channel regions. Some of the shortcomings of this approach include the fact that the level of induced strain can be relaxed in subsequent thermal heating processes, including self-induced heating effects, thereby reducing device performance. In addition, the manufacturing process typically requires complex and costly epitaxial growth process flows, typically requiring several epitaxial growth processes. Moreover, the lattice constant mismatch between materials, which is relied for producing a stress on the channel regions, can lead to junction leakage, reducing device reliability and performance.
In addition, while it is known that a tensile strained channel region improves electron mobility in an NMOS device, hole mobility in a PMOS device may be improved or degraded by both tensile or compressive strain depending on the magnitude of the strain. Therefore introducing appropriate levels of different types of strain into PMOS and NMOS device channel regions on a single process wafer remains a challenge.
There is therefore a need in the semiconductor device integrated circuit (IC) processing art to develop improved strained channel SOI devices and methods for forming the same to improve device performance as well as improving a process flow.
It is therefore an object of the invention to provide improved strained channel SOI devices and a method for forming the same to improve device performance as well as improving a process flow, while overcoming other shortcomings and deficiencies of the prior art.